According to the manual, SSP1601 has these features:

<li> 16-bit fixed point arithmetic
<li> ACC + A x B -> ACC; MAC operation in 40ns using pipelined multiplier
<li> 16x16-bit pipelined multiply with 32-bit output
<li> 32-bit ALU operation
<li> 512-word data RAM; RAM0, RAM1
<li> Eight 8-bit RAM point registers:

R0 ~ R3 for RAM0
R4 ~ R7 for RAM1

<li> RAM pointer registers for easy circular buffer operation
<li> Simple instruction set
<li> User defined I/Os
<li> Up to 64K word Program Memory which can be readable and writable
<li> SSP1601 EVA Chip (additional) has two 256-word SRAM for each RAM bank
<li> 25 MIPS @ 5.0 Volt
<li> 68-pin PLCC (evaluation version
<li> 0.8um double metal CMOS (CSP4H)
<li> Excepted core size (except PAD, Data RAM): 3600um x 2400um