<table width=\'90%\' cellspacing=\'0\'><tr style=\'background-color: #224422\' style=\'padding-left: 5px; padding-right: 5px; text-align: center;\'><th>Name</th><th>Number</th><th>I/O</th><th>Description</th></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>CK1</center></td><td><center>51</center></td><td><center>I</center></td><td>Clock</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>PH10B</center></td><td><center>52</center></td><td><center>O</center></td><td>Internal clock output<br>Inverted output of PH1 generated from CK1</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>RESB</center></td><td><center>50</center></td><td><center>I</center></td><td>Asynchronous step<br>Effective when SK1 is rising</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>SS</center></td><td><center>53</center></td><td><center>I</center></td><td>Asynchronous single step<br>Effective when CK1 of a cycle is rising</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>INT0<br>INT1<br>INT2</center></td><td><center>56<br>57<br>58</center></td><td><center>I</center></td><td>Interrupt request 0<br>Interrupt request 1<br>Interrupt request 2</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>PA0-PA15</center></td><td><center>27-35 & 37-43</center></td><td><center>O</center></td><td>Program address</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>PD0-PD15</center></td><td><center>11-26</center></td><td><center>I/O</center></td><td>Program data</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>EXT0-EXT15</center></td><td><center>1-9 & 61-68</center></td><td><center>I/O</center></td><td>External data bus</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>EA0-EA2</center></td><td><center>44-46</center></td><td><center>O</center></td><td>External register address</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>ESB</center></td><td><center>47</center></td><td><center>O</center></td><td>External data strobe</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>R/WB</center></td><td><center>48</center></td><td><center>O</center></td><td>Read/write timing signal for EXT bus</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>USR0<br>USR1</center></td><td><center>54<br>55</center></td><td><center>I</center></td><td>User input 0<br>User input 1</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>VDD</center></td><td><center>36, 49</center></td><td><center>I</center></td><td>+5 Volt</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>VSS</center></td><td><center>&nbsp;</center></td><td><center>I</center></td><td>GND</td></tr><tr style=\'background-color: #002200\' style=\'padding-left: 5px; padding-right:5px;\'><td><center>ST5<br>ST6</center></td><td><center>59<br>60</center></td><td><center>O</center></td><td>User output 0<br>User output 1</td></tr></table>